Consider the following data path diagram with registers MAR, MDR, IR, PC, R0-R7, TEMP1, TEMP2, ALU,

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GATE-CS is a competitive examination conducted in India. This question is from the 2020 GATE-CS Computer Organization and Architecture paper.

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This GATE-CS 2020 Computer Organization and Architecture question has a medium difficulty level and is marked as an important question.

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Question

Consider the following data path diagram with registers MAR, MDR, IR, PC, R0-R7, TEMP1, TEMP2, ALU, and a shared BUS. Consider the instruction: R0 <-- R1 + R2. The following steps are used to execute it. The subscripts r and w indicate read and write operations.1. R2r, TEMP1r, ALUadd, TEMP2w2. R1r, TEMP1w3. PCr, MARw, MEMr4. TEMP2r, R0w5. MDRr, IRwWhich one of the following is the correct order of execution of the above steps?

Accepted Answer

Correct Answer: (A) 3, 5, 2, 1, 4Concept -- Instruction Execution Cycle in a Data Path: Instruction execution follows the Fetch-Decode-Execute cycle. Step 3 (PCr, MARw, MEMr): Fetch phase -- the PC value is sent to MAR, and memory is read to get the instruction. This must happen first. Step 5 (MDRr, IRw): Decode phase -- the fetched instruction in MDR is loaded into the Instruction Register for decoding. This follows step 3. Step 2 (R1r, TEMP1w): Execute phase part 1 -- R1 is loaded into TEMP1 for the ALU operation. Step 1 (R2r, TEMP1r, ALUadd, TEMP2w): Execute phase part 2 -- R2 and TEMP1 are read, the ALU adds them, and the result is stored in TEMP2. Step 4 (TEMP2r, R0w): Write-back -- the result in TEMP2 is written to R0. The correct order is 3, 5, 2, 1, 4.

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