A processor has 64 registers and uses a 16-bit instruction format. It has two types of instructions:

Q: What is GATE-CS?

GATE-CS is a competitive examination conducted in India. This question is from the 2020 GATE-CS Computer Organization and Architecture paper.

Q: How can I prepare for GATE-CS Computer Organization and Architecture?

To prepare for GATE-CS Computer Organization and Architecture, practice previous year questions (PYQs), understand concepts thoroughly, and solve mock tests regularly. This 2020 question covers Machine Instructions and Addressing Modes topic.

Q: What is the difficulty level of this question?

This GATE-CS 2020 Computer Organization and Architecture question has a hard difficulty level and is marked as an important question.

Q: Where can I find more GATE-CS previous year questions?

You can find more GATE-CS previous year questions on AspirantMitraa. Browse by subject, topic, year, and difficulty level to practice effectively.

Question

A processor has 64 registers and uses a 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _____

Accepted Answer

Answer: 14Concept -- Instruction Format and Opcode Allocation: Total instruction width = 16 bits. 64 registers require log2(64) = 6 bits per register field. I-type format: opcode + 1 register (6 bits) + 4-bit immediate. Bits used by register and immediate = 6 + 4 = 10 bits. Bits for I-type opcode = 16 - 10 = 6 bits. With 8 I-type opcodes, 3 bits are needed to represent them, but the opcode field is 6 bits total. If the most significant bit of the 6-bit opcode is 0 for I-type and 1 for R-type (using 1 bit to distinguish type), then I-type uses 5 remaining bits for the actual opcode (allowing up to 2^5 = 32 opcodes, but only 8 are used). For R-type: opcode + 2 registers (6+6=12 bits) = 12 bits for registers. Opcode bits = 16 - 12 = 4 bits. If the type-distinguishing bit is included in the 4-bit opcode field with MSB=1, then 3 bits remain for R-type opcode encoding, giving 2^3 = 8 R-type opcodes. However, the answer 14 arises from a different calculation where the total opcode space is split: with 1 type-distinguishing bit, there are 2 categories; the opcode field for I-type uses more bits. Following the standard approach: opcode field = 16 - (non-opcode bits); I-type: 16 - 6 - 4 = 6 bits for opcode. R-type: 16 - 6 - 6 = 4 bits for opcode. I-type takes 8 of the available 2^6=64 codewords from the 6-bit opcode space. For R-type with 4-bit opcode, 2^4=16 possible codes, but collisions must be avoided. With 6-bit I-type opcodes (8 used) and 4-bit R-type opcodes: the leading 4 bits of the 6-bit I-type opcode are 0000 to 0111 (for 8 I-type codes, the first 4 bits cycle through patterns). R-type 4-bit opcodes must avoid patterns 0000-0111 (already used partially by I-type top-4 bits). Available R-type opcodes: all 16 minus 2 (those whose 4-bit code is 0000 or 0001, which overlap with I-type top 4 bits of 0000 and 0001 for 8 I-type codes spanning top-4 bits 0000 and 0001). 16 - 2 = 14. Answer: 14.

Master GATE-CS with Our Test Series

More Questions from Machine Instructions and Addressing Modes

Frequently Asked Questions

Master GATE-CS with Our Test Series

More Questions from Machine Instructions and Addressing Modes

Frequently Asked Questions