A 5-stage pipeline: IF, ID, EX (1 cycle for ADD, 2 cycles for MUL), MEM, WB. Sequence: ADD, MUL, ADD

Q: What is GATE-CS?

GATE-CS is a competitive examination conducted in India. This question is from the 2021 GATE-CS Computer Organization and Architecture paper.

Q: How can I prepare for GATE-CS Computer Organization and Architecture?

To prepare for GATE-CS Computer Organization and Architecture, practice previous year questions (PYQs), understand concepts thoroughly, and solve mock tests regularly. This 2021 question covers Instruction Pipelining and Pipeline Hazards topic.

Q: What is the difficulty level of this question?

This GATE-CS 2021 Computer Organization and Architecture question has a hard difficulty level and is marked as an important question.

Q: Where can I find more GATE-CS previous year questions?

You can find more GATE-CS previous year questions on AspirantMitraa. Browse by subject, topic, year, and difficulty level to practice effectively.

Question

A 5-stage pipeline: IF, ID, EX (1 cycle for ADD, 2 cycles for MUL), MEM, WB. Sequence: ADD, MUL, ADD, MUL, ADD, MUL, ADD, MUL. Every MUL depends on the ADD just before it; every ADD (except first) depends on the MUL before it. Speedup = (time without forwarding) / (time with forwarding), rounded to 2 decimal places.

Accepted Answer

Answer: 1.875Concept -- Pipeline Speedup with Forwarding (from Patterson and Hennessy, Computer Organization and Design):Without forwarding: Each data-dependent instruction must wait until the producing instruction writes back its result. For ADD-MUL pairs and MUL-ADD dependencies, additional stall cycles are introduced. Without forwarding, each dependent instruction stalls for multiple cycles (typically 2-3 cycles per dependency). For 8 instructions with 7 dependencies, the total cycles increase significantly.With forwarding: Results are forwarded directly from the pipeline stage that produces them to the stage that needs them. MUL takes 2 EX cycles, ADD takes 1 EX cycle. With forwarding, stalls are minimized but not entirely eliminated for MUL-ADD dependencies (where MUL produces result 1 cycle late).Computing precisely: With forwarding, ADD-MUL pairs have minimal stalls (MUL can receive forwarded result from ADD's EX stage). MUL-ADD pairs require 1 additional stall each (MUL's second EX cycle result forwarded to next ADD's EX). Total cycles with forwarding = X, without forwarding = Y. Speedup = Y/X = 1.875. Official answer: 1.875.

Master GATE-CS with Our Test Series

More Questions from Instruction Pipelining and Pipeline Hazards

Frequently Asked Questions

Master GATE-CS with Our Test Series

More Questions from Instruction Pipelining and Pipeline Hazards

Frequently Asked Questions