Consider a 5-stage pipelined processor with IF, ID, EX, MEM, and WB stages. Which of the following s

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GATE-CS is a competitive examination conducted in India. This question is from the 2024 GATE-CS Computer Organization and Architecture paper.

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This GATE-CS 2024 Computer Organization and Architecture question has a medium difficulty level and is marked as an important question.

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Question

Consider a 5-stage pipelined processor with IF, ID, EX, MEM, and WB stages. Which of the following statements about forwarding is/are CORRECT?(A) In a pipelined execution, forwarding means the result from a source stage of an earlier instruction is passed on to the destination stage of a later instruction.(B) In forwarding, data from the output of the MEM stage can be passed on to the input of the EX stage of the next instruction.(C) Forwarding cannot prevent all pipeline stalls.(D) Forwarding does not require any extra hardware to retrieve the data from the pipeline stages.

Accepted Answer

Correct Answer: (A), (B), and (C)Concept -- Data Hazards and Forwarding (from Patterson and Hennessy, Computer Organization and Design):(A) TRUE: Forwarding (also called bypassing or short-circuiting) is the technique of routing a computed result directly from the pipeline register of an earlier instruction's stage to the input of a later instruction's stage, without waiting for the result to be written back to the register file. This is the standard definition from Patterson and Hennessy.(B) TRUE: A load-use forwarding path (MEM to EX) is a standard forwarding path. After a load instruction completes its MEM stage, the loaded value can be forwarded to the EX stage of the instruction following the load (if it is not a load-use hazard requiring a stall). More generally, MEM --> EX forwarding is valid for ALU results too.(C) TRUE: Forwarding cannot eliminate the load-use hazard (also called a load-use data hazard). If instruction I2 immediately follows a load instruction I1 and uses the loaded value, I2 must stall for one cycle because the data is not available until after MEM of I1, but I2 needs it at the beginning of EX. One pipeline bubble (stall) is unavoidable in this case even with forwarding.(D) FALSE: Forwarding requires additional hardware: pipeline registers to hold intermediate values, multiplexers (MUXes) at the inputs of the EX stage to select between the register file output and forwarded values, and a hazard detection unit to identify when forwarding is needed and control the MUXes. This extra hardware is non-trivial.

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