A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is en

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Question

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?ADD R1, #25 // R1 = R1 + 25

Accepted Answer

Correct Answer: (B) 20Concept — Instruction Format and Field Sizes: An instruction word of fixed size must allocate its 32 bits among the opcode, register specifiers, and operand fields. The goal is to determine how many bits remain for the immediate operand.Step 1 — Opcode bits:Number of distinct instruction types = 50. We need ⌈log₂(50)⌉ bits. Since 2⁵ = 32 6 bits for the opcode.Step 2 — Register specifier bits:Number of registers = 64 = 2⁶. Addressing one register requires 6 bits. The instruction ADD R1, #25 has one register operand (R1).Step 3 — Immediate operand bits:Total instruction size = 32 bits.Immediate bits = 32 − opcode bits − register bits= 32 − 6 − 6 = 20 bitsInstruction layout:| Opcode (6) | Register R1 (6) | Immediate #25 (20) | = 32 bits totalWhy other options are wrong:Option A (16): Would require only 4+4 bits for opcode+register, which is too few to encode 50 instructions and 64 registers.Option C (22) and D (24): Would leave insufficient bits for the required opcode and register fields.

A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?ADD R1, #25 // R1 = R1 + 25

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A processor has 64 general-purpose registers and 50 distinct instruction types. An instruction is encoded in 32-bits. What is the maximum number of bits that can be used to store the immediate operand for the given instruction?ADD R1, #25 // R1 = R1 + 25

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