A system has cache memory (addressed by physical address) and an MMU with TLB. When a page is evicte

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GATE-CS is a competitive examination conducted in India. This question is from the 2026 GATE-CS Operating Systems paper.

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To prepare for GATE-CS Operating Systems, practice previous year questions (PYQs), understand concepts thoroughly, and solve mock tests regularly. This 2026 question covers Memory Management and Virtual Memory topic.

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This GATE-CS 2026 Operating Systems question has a hard difficulty level and is marked as an important question.

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Question

A system has cache memory (addressed by physical address) and an MMU with TLB. When a page is evicted from main memory, corresponding cache blocks are marked invalid. For a given memory reference, which of the following sequences of events can NEVER happen?(A) TLB miss, Page table hit, Cache hit.(B) TLB hit, Page table miss, Cache hit.(C) TLB miss, Page table miss, Cache hit.(D) TLB miss, Page table miss, Cache miss.

Accepted Answer

Correct Answer: (B) and (C)Concept -- TLB, Page Table, and Cache Interaction: A: TLB miss (page not in TLB), page table hit (page is in main memory), cache hit (the data block is in cache) — possible. B: TLB hit means the page is mapped and present in memory (since TLB entries are valid only for pages in memory). Page table miss means the page is not in memory (page fault). These are contradictory — impossible. C: TLB miss + page table miss means the page is not in memory (page fault). If the page is not in memory, its data cannot be in the cache because the problem states that when a page is evicted, corresponding cache blocks are marked invalid. Thus a cache hit cannot occur. Impossible. D: TLB miss + page table miss + cache miss is the normal page fault scenario — possible. Hence B and C can never happen.

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