A non-pipelined instruction execution unit operates at 1.6 GHz and takes an average of 5 clock cycle

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GATE-CS is a competitive examination conducted in India. This question is from the 2026 GATE-CS Computer Organization and Architecture paper.

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To prepare for GATE-CS Computer Organization and Architecture, practice previous year questions (PYQs), understand concepts thoroughly, and solve mock tests regularly. This 2026 question covers Instruction Pipelining and Pipeline Hazards topic.

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This GATE-CS 2026 Computer Organization and Architecture question has a medium difficulty level and is marked as an important question.

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Question

A non-pipelined instruction execution unit operates at 1.6 GHz and takes an average of 5 clock cycles to complete an instruction. To improve performance, the system was pipelined with a goal of 1 instruction per clock cycle, but could only operate at 1.2 GHz due to pipeline overheads. While executing a program, 30% of instructions encountered a stall of 2 cycles due to pipeline hazards. The speed-up obtained by the pipelined design over the non-pipelined one for this program is ___________. (rounded off to two decimal places)Note: 1G = 10^9

Accepted Answer

Answer: 2.35Concept -- Pipeline Speedup with Stalls: Non-pipelined: CPI = 5, clock rate = 1.6 GHz → time per instruction = 5 / (1.6×10^9) = 3.125 ns.Pipelined: clock rate = 1.2 GHz → cycle time = 1/1.2 ns = 0.83333 ns. Ideal CPI = 1. But 30% of instructions cause a stall of 2 cycles. So average CPI = 1 + 0.3×2 = 1.6. Time per instruction = 1.6 × (1/1.2) ns = 1.6/1.2 = 1.3333 ns.Speedup = non-pipelined time / pipelined time = 3.125 / 1.3333 = 2.34375 ≈ 2.34 (or 2.35 when rounded).Note: Speedup = (CPI_nonpipe × cycle_time_nonpipe) / (CPI_pipe × cycle_time_pipe). Pipeline hazards increase CPI above 1. The formula accounts for stalls.

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